1. Field of the Invention
The present invention is directed generally to hierarchical cache memory structures.
2. Description of the Background
In a computer, the central processing unit (CPU) executes instructions at a predetermined rate. To obtain the instructions to be executed, or the data which is to be manipulated, the CPU must access a memory which contains the necessary instructions and data. Such memory is typically one of two types. A static random access memory (SRAM) is characterized by operation in one of two mutually-exclusive and self-maintaining states. Each static memory cell typically has an output which reflects a "high" voltage or "low" voltage representative of a logic level "1" or a logic level "0", respectively.
Another type of memory is the dynamic random access memory (DRAM) which does not have stable states of operation. A DRAM, like an SRAM, can be programmed to store a voltage which represents a logic level "1" or a logic level "0" but requires periodic refreshing to maintain those logic levels for more than a very short period of time. Despite that limitation, DRAMs are frequently used because of the significantly greater packing density which can be obtained, and because of the substantially lower cost associated therewith. Thus, in a computer, it is not unusual to find that the large main memory is comprised of DRAMs.
Because a CPU operating in conjunction with a main memory constructed of DRAMs will operate at a substantially faster speed than such a main memory, a smaller cache memory, typically constructed of SRAMs, is often used to buffer the data and the instructions between the main memory and the CPU. The cache memory is typically managed under hardware control and maintains a copy of certain portions of the information found in the main memory. The information maintained in the cache memory are those instructions and data which the CPU is likely to use. Thus, because the CPU can often find the instructions and data needed in the faster cache memory, the speed at which the CPU can operate is no longer limited to the access time of the main memory.
Despite the use of SRAM cache memory, CPU's still operate faster than instructions and data can be provided thereto. Recently, CPU's have been introduced that have execution cycle times under five nanoseconds, which is below the access time of typical SRAMs. To enable such fast CPU's to operate more efficiently, "on-chip" cache memories provide an additional level of cache memory between the processor and the external SRAM cache memory. The use of such on-board cache memory creates a hierarchical situation between the on-board cache memory and the external cache memory. That hierarchical arrangement allows the CPU to operate more quickly because the data and instructions required by the CPU are likely to be found in one of the cache memories. However, the need still exists to provide memory devices which have faster access times so that external cache memory constructed of SRAMs may allow CPU's to operate as close as possible to their limits.